Cadence says its AI-based chip design tools deliver a process node’s worth of performance gain, but without moving to a new node

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Cadence CEO Anirudh Devgan recently noted that the company’s AI-assisted chip design tools enable chip performance and density benefits similar to transitioning to a next-generation process node, but without moving to a new node . Devgan cited strong improvements in performance, power and area (PPA), the most important metrics for chipmakers (along with cost), and also cited dramatic productivity improvements and examples with the company’s custom processors.

Discussing EDA’s latest suite of AI-assisted software tools, Devgan said, “So overall, we’re happy with the benefits we’re getting, especially the PPA improvement. And productivity improvements can be anywhere from 5x to 10x, but the benefits of PPA are truly remarkable and almost equivalent to a single node type. Migrating a single process node typically achieves a 15% to 20% PPA improvement, and we can achieve that with AI.”

“As you probably know, we have five major AI platforms (in the Cadence.AI portfolio), analog, digital, verification, PCB and package and system analysis, it’s quite a rich portfolio,” said Anirudh Devgan, chief executive of Cadence. , during the company’s earnings conference call with analysts and investors (via Looking for Alpha). “Customers typically see a 5% to 20% improvement in PPA, which is significant.”

Modern process technologies give rather limited node-to-node performance and transistor density scaling. Compared to TSMC N5 (a 5nm process technology), the company’s N3 (a 3nm node) offers a 10% to 15% performance improvement, and TSMC promises a similar improvement for N2 compared to N3 . Therefore, achieving a performance increase of up to 20% simply by using a set of AI-optimized tools is a very significant achievement, akin to a step forward to a new node.

Cadence is primarily known for its electronic design automation (EDA), simulation and prototyping software for chip development. However, not everyone knows that the company also designs its own Palladium processors, some of the most complex chips built by TSMC, to speed up simulation workloads. Improving the performance and increasing the transistor density of these Palladium processors is of critical importance to Cadence, both from a competitive and cost perspective. Therefore, the company uses its own tools to refine the design of these processors and get these benefits as well.

“We also apply our own solutions internally,” added Devgan. “So these are true comparisons between AI and non-AI solutions. So even in the latest Palladium Z3 chip, we saw a 15% improvement in power using Cadence Cerebrus. In the most recent AI IP we designed, we saw anywhere from a 13% to 20% improvement in our IP pool using our own Cadence.AI solutions, which is very consistent with what we’re seeing with customers top notch.”

Beyond the PPA improvements, the company claims that Cadence’s AI tools generate substantial productivity increases, often ranging from 5 to 10 times typical output. If confirmed, this level of efficiency should make the Cadence.AI portfolio a very compelling proposition for an industry that needs to build more sophisticated designs that deliver higher performance than their predecessors while managing costs.